An integrated circuit memory, such as a static random access memory (SRAM), is generally implemented as an array of memory cells in a plurality of rows and columns. An array may be subdivided into blocks of memory cells. The memory cells are addressable through block, row, and column decoders for reading data from the memory cells or writing data into the memory cells. Each memory cell has a unique address at an intersection of a row and a column. The bit line pairs are commonly used for both reading data from, and writing data into, the memory cell. Typically, data is read from memory when a write enable signal is at a logic high (or inactive), and written into memory when the write enable signal is at a logic low, (or active).
During a read cycle, a word line selects the addressed row of memory cells, and a pair of complementary bit lines communicate the data bit between the addressed row and a sense amplifier. The data exists as a relatively small differential voltage on the pair of complementary bit lines. The differential voltage on the bit line pairs may be as little as 80 millivolts. The column address determines which sense amplifier detects and amplifies the differential voltage and communicates it to a read global data line pair. The read global data line pair then carries the data to the output multiplexers, where it is directed to an output buffer/driver and on to the data pad. The output buffer/driver converts the data bit from a differential signal to a single-ended signal and drives the output data pad to the correct output logic level, depending on which logic family is used.
There are various logic families available from which to choose when designing an integrated circuit memory. Each logic family has advantages and disadvantages. ECL (emitter-coupled logic) is one logic family that uses bipolar transistors. CMOS is another type of integrated circuit logic, however CMOS uses complementary MOSFET (metal-oxide semiconductor field-effect transistor) transistors. ECL circuits have the advantage of high speed, but they consume a large amount of power. CMOS logic circuits have the advantages of low power dissipation, high input resistance, low output resistance, and low noise generation. For an ECL circuit, the swing between high and low logic states is only about one base-emitter diode voltage drop (V.sub.EE). In contrast, CMOS logic states may swing the full rail of the power supply voltage. BICMOS circuits are constructed by including bipolar transistors and CMOS transistors on the same integrated circuit. Therefore, a BICMOS logic circuit can operate at high speed without consuming a large amount of power.
When a memory using ECL as the logic family for the output signal is in a write cycle, some of the data output circuitry, including the data output buffers and sense amplifiers, are disabled and the differential data signals are equalized at a predetermined voltage level. When entering a read cycle from a write cycle, (sometimes called a first read, or a write recovery read) the data output circuits have to be reactivated. The data output buffers are reactivated by an output enable signal that is provided when the write enable signal becomes inactive (beginning a read cycle).
A conventional data output buffer includes a differential amplifier for receiving differential data signals and for providing a single-ended data output signal. A wired-OR connected input transistor for receiving the output enable signal may also be included. During the write cycle, the differential amplifier is disabled by providing the output enable signal to the base of the wired-OR connected input transistor at a voltage higher than the equalized differential data signals. This causes the current in the differential amplifier to be steered through the wired-OR connected transistor, thus causing the single-ended data output signal to be provided at a predetermined voltage, usually determined by the specification requirements. The conventional method of enabling the data output buffers during a write cycle to read cycle transition is to decrease the output enable signal below the lowest voltage of the pair of differential data signals so that no current is steered through the wired-OR connected transistor. The data output buffers are enabled when the output enable signal decreased below the voltage of the differential data signals. If the output enable signal is decreased too soon, a single-ended data signal is provided before a valid differential data signal is received by the data output buffer. Since differential data signals may still be equalized, the voltage level of the single-ended data signal may drift to the midpoint of the ECL output level, and then be driven to a ECL logic high or ECL logic low. This drifting greatly increases to the output rise time and may be undesirable in some applications. If the output enable signal is provided later, to ensure that valid differential data signals are presented to the data output buffer, undesirable access time delay may occur. Therefore, the timing of the output enable signal is very important.
The conventional method for ensuring the correct timing of the output enable signal is to simply adjust the propagation delay of the output enable signal until it arrives at the data output buffer at the correct time. That is, the effective lengths of the signal paths are determined to ensure that the output enable signal arrives to enable the output buffer at the proper time, just before the data signal arrives. But, as integrated circuit memories become larger and faster, adjusting the timing of the various signals within the memory becomes increasingly difficult.